The present invention relates to a semiconductor device having a multilayer interconnection structure and a method for fabricating the semiconductor device, more specifically a semiconductor device having a multilayer interconnection structure using low dielectric constant (low-k) films as the inter-layer insulation films and a method for fabricating the semiconductor device.
The recent increasing micronization of semiconductor devices requires decrease of the interconnection resistance and interconnection capacitance of the semiconductor devices.
To meet such requirement, the main material of the interconnections is shifting from Al (aluminum) to Cu (copper) having lower relative resistance and better electromigration characteristics. Accompanying the shift of the major material of the interconnections to Cu, the process for forming the interconnections is shifting from the processing of depositing the interconnection materials and patterning them by lithography and dry etching as of RIE (Reactive Ion Etching) or others to the so-called damascene process (refer to, e.g., Japanese Patent Application Unexamined Publication No. 2001-298084). In the damascene process, trench patterns and hole patterns are formed in the interconnection insulation films, and the interconnection material is buried in the trenches and holes. The shift of the forming process to the damascene process accompanying the shift of the interconnection material to Cu is because Cu is difficult to process by RIE, while Al is not.
As the materials of the inter-layer insulation films for the insulation between the interconnections, SiO2, FSG (fluorinated silicate glass), etc. have been so far used.
As a countermeasure to the interconnection delay due to the recent micronization, decrease of the interconnection resistance and interconnection capacitance is required. However, it is difficult to further lower the resistance of the interconnections formed of Cu as the major material. It is being studied to use as the inter-layer insulation films low-k films whose dielectric constants are lower than silicon oxide film and silicon nitride film to thereby decrease the interconnection capacitance.
As semiconductor elements are increasingly micronized, a number of transistors to be mounted on a chip is on increase and is even 100M pieces. The interconnection layers interconnecting the transistors and supplying power sources are required to have various functions. That is, the source interconnections are required to be the interconnections of low resistance for making the voltage decreases small. The interconnections interconnecting short distances are required to be micronized interconnections for higher circuit densities. The interconnections interconnecting circuit blocks are required to have lower resistance than the micronized interconnections and have pitches whish are more micronized than the upper interconnection layers.
In the multilayer interconnection structure of semiconductor devices, in order to satisfy such various requirements of these interconnection layers, interconnection layer parts each formed of a plurality of layers and divided in functions, such as a lower layer interconnection which can define micronized pitches, an intermediate layer interconnection used as the interconnections among circuit blocks, and an upper layer interconnection used as source interconnections, clock interconnection, etc., are put together.
FIG. 17 is a sectional view of a semiconductor device having the conventional multilayer interconnection structure, which shows the structure thereof.
A device isolation film 302 for defining a device region is formed on a silicon substrate 300. A MOS transistor including a gate electrode 304 and source/drain diffused layers 306 is formed in the device region of the silicon substrate 300.
An inter-layer insulation film 310 with a contact plug 308 buried in is formed on the silicon substrate 300 with the MOS transistor formed on.
On the inter-layer insulation film 310 with the contact plug 308 buried in, an inter-layer insulation film 312 is formed of a silicon nitride film and one of a silicon oxide film or an FSG film laid on the silicon nitride film. In the region of the inter-layer insulation film 312, which includes the contact plug 308, an interconnection layer 314a of a barrier metal layer of a Ta (tantalum) film and a Cu (copper) film is buried, connected to the contact plug 308. An interconnection layer 314b of the barrier metal layer of the tantalum film and the Cu film is buried in the other region of the inter-layer insulation film 312.
On the inter-layer insulation film 312 with the interconnection layers 314a, 314b buried in, an inter-layer insulation film 316 is formed of a silicon nitride film and one of a silicon oxide film or an FSG film laid on the silicon nitride film. An inter-layer insulation film 318 is formed of a silicon nitride film and one of a silicon oxide film or an FSG film laid on the silicon nitride film. In the regions of the inter-layer insulation films 316, 318 on the interconnection layer 314a, an interconnection layer 320a of a barrier metal layer of a tantalum film, and a Cu film is buried, connected to the interconnection layer 314a with the via portion buried in the inter-layer insulation film 316 and with the interconnection portion buried in the inter-layer insulation film 318. In the region of the inter-layer insulation film 318 over the interconnection layer 314b, an interconnection layer 320b of a barrier metal layer of a tantalum film, and a Cu film is buried.
On the interconnection layer 318 with the interconnection layers 320a, 320b buried in, an inter-layer insulation film 322 is formed of a silicon nitride film and one of a silicon oxide film or an FSG film laid on the silicon nitride film. On the inter-layer insulation film 322, an inter-layer insulation film 324 is formed of a silicon nitride film and one of a silicon oxide film or an FSG film laid on the silicon nitride film. In the regions of the inter-layer insulation films 322, 324 on the interconnection layer 320a, an interconnection layer 326a of a barrier metal layer of a tantalum film, and a Cu film is buried, connected to the interconnection layer 320a with the via portion buried in the inter-layer insulation film 322 and with the interconnection portion buried in the inter-layer insulation film 324. In the region of the inter-layer insulation film 324 over the connection layer 320b, an interconnection layer 326b of a barrier metal layer of a tantalum film, and a Cu film is buried.
On the interconnection layer 324 with the interconnection layers 326a, 326b buried in, an inter-layer insulation film 328 is formed of a silicon nitride film and one of a silicon oxide film or an FSG film laid on the silicon nitride film. On the inter-layer insulation film 328, an inter-layer insulation film 330 is formed of a silicon nitride film and one of a silicon oxide film or an FSG film laid on the silicon nitride film. In the regions of the inter-layer insulation films 328, 330 on the interconnection layer 326a, an interconnection layer 332a of a barrier metal layer of a tantalum film, and a Cu film is buried, connected to the interconnection layer 326a with the via portion buried in the inter-layer insulation film 328 and with the interconnection portion buried in the inter-layer insulation film 330. In the region of the inter-layer insulation film 330 over the connection layer 326b, an interconnection layer 332b of a barrier metal layer of a tantalum film, and a Cu film is buried.
Thus, the lower interconnection part having the four-layer multilayer interconnection structure of the interconnection layers 314a, 314b, the interconnection layers 320a, 320b, the interconnection layers 326a, 326b and the interconnection layers 332a, 332b is formed on the silicon substrate 300.
On the interconnection layer 330 with the interconnection layers 332a, 332b buried in, an inter-layer insulation film 334 is formed of a silicon nitride film and one of a silicon oxide film or an FSG film laid on the silicon nitride film. On the inter-layer insulation film 334, an inter-layer insulation film 336 is formed of a silicon nitride film and one of a silicon oxide film or an FSG film laid on the silicon nitride film. In the regions of the inter-layer insulation films 334, 336 on the interconnection layer 332a, an interconnection layer 338a of a barrier metal layer of a tantalum film, and a Cu film is buried, connected to the interconnection layer 332a with the via portion buried in the inter-layer insulation film 334 and with the interconnection portion buried in the inter-layer insulation film 336. In the region of the inter-layer insulation film 336 over the connection layer 332b, an interconnection layer 338b of a barrier metal layer of a tantalum film, and a Cu film is buried.
On the interlayer insulation film 336 with the interconnection layers 338a, 338b buried in, an inter-layer insulation film 340 is formed of a silicon nitride film and one of a silicon oxide film or an FSG film laid on the silicon nitride film. On the inter-layer insulation film 340, an inter-layer insulation film 342 is formed of a silicon nitride film and one of a silicon oxide film or an FSG film laid on the silicon nitride film. In the regions of the inter-layer insulation films 340, 342 on the interconnection layer 338a, an interconnection layer 344a of a barrier metal layer of a tantalum film, and a Cu film is buried, connected to the interconnection layer 338a with the via portion buried in the inter-layer insulation film 340 and with the interconnection portion buried in the inter-layer insulation film 342. In the region of the inter-layer insulation film 342 over the connection layer 338b, an interconnection layer 344b of a barrier metal layer of a tantalum film, and a Cu film is buried.
Thus, the upper interconnection part having the two-layer multilayer interconnection structure of the interconnection layers 338a, 338b and the interconnection layers 344a, 344b having interconnection patterns of a larger pitch than the interconnection layers 314a, 314b, the interconnection layer 320a, 320b, the interconnection layer 326a, 326b and the interconnection layers 332a, 332b of the lower interconnection part is formed on the lower interconnection part.
On the inter-layer insulation film 342 with the interconnection layers 344a, 344b buried in, an inter-layer insulation film 346 is formed of a silicon oxide film laid on a silicon nitride film. Contact plugs 348 are buried in the inter-layer insulation film 346.
On the region of the inter-layer insulation film 346 containing the contact plugs 348, an electrode 350 is formed, connected to the interconnection layer 344a through the contact plugs 348.
On the inter-layer insulation film 346 with the electrode 350 formed on, a cover film 352 is formed of a silicon nitride film 352a formed on a silicon oxide film 352b. An opening 354 is formed in the cover film 352 down to the electrode 350.
In the case that the interconnection layers are divided in terms of functions as described above, the structures of the respective interconnection layers are changed in accordance with required characteristics.
For example, the lower layer interconnections are formed at small pitches, and to decrease the interconnection capacitance, film thicknesses of the interconnection layers are made small. In order to decrease the interconnection capacitance, materials of the inter-layer insulation films must be low-k materials.
On the other hand, the upper layer interconnections are formed at larger interconnection pitches so as to allow the interconnections to be formed in a thicker thickness. The interconnection capacitance does not critically matter in the upper interconnection layers, which permits silicon oxide film to be used as the inter-layer insulation films.
The intermediate layer interconnections are required to have characteristics which are middle between the lower layer interconnections and the upper layer interconnections described above. At this time, the intermediate layer interconnections, which interconnect the circuit blocks, have the interconnection length larger than the lower layer interconnections, and the resistance must be made low. Accordingly, the thickness of the interconnection is larger than the lower layer interconnections, and the pitch of the interconnections is larger. The interconnection capacitance increase due to the thick interconnections must be suppressed, and to this end, low-k materials must be used as the material of the inter-layer insulation films.
However, when low-k films are used as the inter-layer insulation films in place of silicon oxide film, etc. for the end of decreasing the interconnection capacitance in the lower layer interconnections and the intermediate layer interconnections, an inconvenience that defects easily take place in the interconnections, which lowers the yield, and others have happened.